Compact and Timing-Efficient GF(28) Multiplier for Reed-Solomon Codes in HQC

초록

Galois field multiplication over GF(28) is a core operation in Reed-Solomon (RS) codes, which form the error-correction layer in code-based post-quantum cryptographic schemes such as Hamming Quasi-Cyclic (HQC). Since RS encoding and decoding involve a number of GF(28) multiplications, the efficiency of these multipliers directly determines the area, throughput, and timing closure of HQC hardware implementations. This paper presents a compact and timing-efficient GF(28) multiplier architecture tailored to HQC's fixed irreducible polynomial f(x)=x8+x4+x3+x2+1. Unlike reconfigurable designs that incur area overhead or sequential multipliers that increase latency, the proposed architecture fixes the polynomial and fully unrolls the computation, enabling one multiplication result per clock cycle. The design achieves both reduced LUT usage and a shortened critical path, resulting in higher maximum operating frequency. Implemented on a Xilinx Artix-7 FPGA, the proposed architecture achieves up to 53% area reduction and 37 % improvement in Fmax compared to state-of-the-art reconfigurable multipliers, while maintaining comparable performance to lightweight LFSR-based designs. These results highlight the practicality of the proposed design as a compact, high-speed building block for Reed-Solomon encoders in HQC accelerators. © 2025 IEEE.

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