VCO 와 Counter 를 사용한 DCPWM CMOS 벅 변환기 설계

초록

The proposed DCPWM CMOS buck converter is designed based on the voltage control oscillator and counter circuit of the digital control block. Set generators and reset generators are designed using a state generator to synchronize all blocks of the proposed circuit with the clock. A method of counting time, a method of detecting a signal of a PFD without an integrator is used. The proposed DCPWM buck converter is designed using CMOS 65nm 6-metal 1-poly process. As a result of measurement of the chip performance, the input voltage range is 1.1V to 1.3V, the output voltage range is 0.3V to 0.6V, the load current range is 50mA up to 200mA, the output voltage ripple Is 60mV, switching frequency is 2MHz, and maximum power efficiency is 91%. The proposed buck converteris expected to be used for power management of mobile and wearable devices.