2단 자체 고리발진기를 이용한 3.3V 고속 CMOS PLL

YOON KWANG SUB

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2단 자체 고리발진기를 이용한 3.3V 고속 CMOS PLL

A 3.3V High Speed CMOS PLL with a Two-stage Self-feedback Ring Oscillator

YOON KWANG SUB

초록

A 3.3V PLL is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency with new VCO with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz-1GHz with a good linearity. The DC-DC voltage Up/Down Converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6um n-well CMOS process. The simulation results show a locking time of 2.6us at 1GHz, lock in range of 100MHz-1GHz, and a power dissipation of 112mW.

제목: 2단 자체 고리발진기를 이용한 3.3V 고속 CMOS PLL

제목 (타언어): A 3.3V High Speed CMOS PLL with a Two-stage Self-feedback Ring Oscillator

저자: YOON KWANG SUB

학회명: 대한전자공학회 CAD 및 VLSI 설계연구회 학술발표회