Design of CMOS reconfigurable operational amplifier for Delta-Sigma Modulator

초록

The proposed CMOS reconfigurable amplifier was employed to implement the fourth order delta-sigma modulator with the oversampling rate of 128, sampling frequency of 256 kHz, and clock frequency of 1.024 MHz for the application of bio signal processing with bandwidth of 1 kHz. The modulator was implemented with the CMOS 180 nm n-well single poly/six metal process. The simulation results demonstrated the SNDR(Signal to Noise and Distortion Ratio) of 86 dB shown , ENOB(Effective Number Of Bit) of 13.9 bits, power consumption of 312 uW, and FoM (Walden Figure of Merit) of 10.2 pJ/step with the input signal frequency of 250 Hz. The modulator utilized the power supply of 1.8V. The effective layout area of the core circuit occupied 800 um x 1200um. The simulation results of the modulator with the proposed reconfigurable amplifier presented better ENOB (5%) and less power consumption (13%) than the previous work. Therefore the proposed reconfigurable amplifier with the time-interleaving technique demonstrated the better performances than the previous works. It is expected that the proposed technique can be applicable to the low power bio-signal processing circuits and systems.