A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor

초록

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 x 450 mu m. Measurement results illustrated a power consumption of 30.7 mu W (analog power: 16.1 mu W and digital power: 14.6 mu W), INL/DNL of -1.8/1.7 LSB, and -0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step.

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