12bits 40MHz pipelined ADC with duty-correction circuit

초록

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a 0.18um CMOS n-well 1 -poly 6-metal process and dissipates 184mW at 1.8V single supply. The SNDR of the proposed libit ADC is 52dB and SFDR of 59dBc (@Fs=20MHz, Fin=1MHz) is measured. Copyright 2008 ACM.