Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin

  • Kim, Munhyeon
  • Lee, Kitae
  • Kim, Sihyun
  • Lee, Jong-Ho
  • Park, Byung-Gook
  • 외 1명
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초록

In this article, for the first time, we proposed the side-shielded forksheet (S-FS) device to sustain extreme device scaling and to expand device design margins. Through the process simulations calibrated based on transmission electron microscopy (TEM) dimensions of the process integration modules, it is verified that n/p-type nanosheet (NS)-shaped stacked channel devices are physically isolated in the S-FS by the dielectric wall formed by the proposed dual liner process scheme (DLS). In addition, distributed correlation is rigorously analyzed by 3-D technology computer aided design (TCAD) device simulations with precisely calibrated models. As a result, it is revealed that the S-FS shows the superior electrical characteristics and design margin compared to the conventional forksheet (C-FS) device when structural variation and work function (WF) fluctuation are considered in extremely scaled devices.

키워드

Logic gatesTinVoltage measurementPerformance evaluationComputational modelingSolid modelingMathematical modelsDevice design marginforksheet devicestacked nanosheet (NS)
제목
Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin
저자
Kim, MunhyeonLee, KitaeKim, SihyunLee, Jong-HoPark, Byung-GookKwon, Daewoong
DOI
10.1109/TED.2022.3156957
발행일
2022-05
유형
Article
저널명
IEEE Transactions on Electron Devices
69
5
페이지
2232 ~ 2235