Design of a 3rd order CMOS sigma-delta modulator with the faster conversion rates using zero-pole Canceling Technique

초록

This paper proposes a new SDM(Sigma Delta Modulator) architecture to improve conversion rates and SNR(Signal-to-noise ratio). The characteristic of the proposed SDM employes an adaptive clocking architecture which includes the first integrator with a 1 MHz clock and the second/third integrator with a 4MHz clock. The SDM circuit with a 0.65um CMOS process is simulated by both MATLAB and Hspice. The simulation results illustrate that SNRs of the proposed SDM are increased by 2dB @ internal 1 bit ADC/DAC and 7dB @ 3bit and 5bit, compared with the conventional SDM.