Study of Gate Overlap Effects on the MoS2 FETs with Graphene S/D electrodes

초록

Two-dimensional (2D) van der Waals (vdW) nanomaterials have been extensively studied as a promising candidates for future electronics due to their excellent physical and electrical properties. Among them, graphene is the most famous 2D material, which has high mobility and a gapless energy band structure. For these reasons, many studies of graphene as a contact electrode have attracted much attention to enhance the ohmic contact property for both n-type and p-type semiconductors based on the gate-induced fermi level modulation of graphene. In this work, the MoS2-based field-effect transistors (FETs), which have graphene source/drain (S/D) electrodes, were investigated to compare with or without the overlap area of a patterned gate electrode and graphene S/D electrodes. First, a patterned metal gate electrode was formed on the Si wafer, and then an h-BN gate insulator, MoS2 channel, and 1st graphene (without gate overlap) S/D were sequentially transferred on it (1st device model). In order to directly compare the gate overlap effect on the same MoS2 FET device, 2nd graphene was attached to the 1st graphene S/D with gate overlap region (2nd device model). In the 1st device model, the MoS2 channel is simultaneously affected by both the p+-Si global gate and the patterned metal gate. The p+-Si global gate pins the Fermi level of the MoS2 channel at the nonoverlap area, and it brings a low drain ON current (ID, ON). However, the overlapped 2nd graphene electrodes protect the Fermi level pinning effect; moreover, it could provide better ohmic contact properties to the MoS2 channel resulting in a higher ID, ON from the fermi level modulation of graphene S/D electrodes.