A CMOS 6-bit 1Gs/s Flash ADC with Input Voltage Range Detection Circuit

초록

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is reported. An input voltage level detector circuit has been designed to overcome the disadvantages of the Flash ADC which consumes most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 79.52mW from 1.2V and achieves 5.1 effective number of bits for input frequency up to 50MHz at 1 GS/s. Therefore it results in 2.32pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.