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초록
This paper introduces a new algorithm on lower power Add-Compare-Selecion (ACS) and Path Metric(PM) normalization for Viterbi Decoder(VD) which can reduce the complexity of computation.
- 제목
- Low Power ACS and PM units implementation for the Viterbi Decoder
- 제목 (타언어)
- 비터비디코더를 위한 저전력 ACS 및 PM units
- 저자
- CHUNG DUCK JIN
- 학회명
- The 2004 International Technical Conference on Circuit/Systems, Computers and Communications(ITC-CSCC2004)