A High-Speed Receiver Architecture for MB-OFDM UWB Communications

초록

This paper presents the architecture design of a receiver for the MB-OFDM UWB communications. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM system including carrier frequency offset and sampling clock offset are analyzed. We then propose a full digital receiver in which all of these issues relevant to the UWB transmission environment are addressed. Novel techniques for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors are proposed. The receiver architecture using 4-parallel synchronization unit is then analyzed. The overall performance degradation of the proposed receiver is simulated to be with maximum 3.08 dB of the ideal receiver in maximum frequency/sampling clock offset tolerance.