Verilog-A를 이용한 고해상도 파이프라인 ADC의 모델링

초록

This paper describes a behavioral modeling of high-resolution Pipeline ADC. In order to demonstrate a importance of modeling with Verilog-A, 12bit Pipeline ADC is modelled and simulated. The ADC employs a 1.5bit architecture per stage and possesses a 12 bit resolution at 80M sampling rate. The proposed set of models takes into account most of Pipeline ADC's non-idealities. For each sub-blocks we present a description of the considered results as well as all of the implemental details.