Design of 12 Bit 500MHz CMOS Current-Mode DAC With Deglitch Circuit

YOON KWANG SUB

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Design of 12 Bit 500MHz CMOS Current-Mode DAC With Deglitch Circuit

12비트 500MHz CMOS 전류구동 DAC 회로 설계

YOON KWANG SUB

초록

This paper described a 12 bit 500MHz CMOS current-mode Digital to Analog Converter(DAC) consisting of 6 MSB current cell matrix stage, 2 MSB unary current source stage, and 4 LSB binary weighting stage.

제목: Design of 12 Bit 500MHz CMOS Current-Mode DAC With Deglitch Circuit

제목 (타언어): 12비트 500MHz CMOS 전류구동 DAC 회로 설계

저자: YOON KWANG SUB

학회명: AWAD 2003