A 3.3V-65MHz 12Bit CMOS Digital to Analog Converter

초록

This paper describes a 3.3V-65MHz 12 bit CMOS current-mode DAC designed with a 8 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors casued by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch has been employed. The simulation results of the designed DAC show a conversion rate of 65MHz, a power dissipation of 71.7mW, a DNL of +/-0.2LSB and an INL of +/-0.8LSB with a single power supply of 3.3V for a CMOS 0.6um n-well technology.