기가 비트 디램을 위한 3차원 구조 모델링에 대한 연구

초록

In this paper, we present a 3D topography simulator, named as 3D-SURFILER(SURface proFILER), to model a complicated 3D structure on the substrate for gigabit DRAMs. The 3D-SURFILER comprises a film deposition module and an dry etching module to figure out the topographical evolution of the wafer. In this work, an MIS (metal-insulator-semicunductor) cylindrical concave capacitor was chosen to verify the accuracy of the simulator.