가중 인코딩 수를 이용한 직렬 십진 고정소수점 곱셈기 설계

초록

In this paper, using a simple multiple of the decimal serial multiplier to reduce the time delay is proposed. The proposed multiplier reduces the delay time by encoding a multiplier to signed digit number of limited range and by generating a simple multiple of the corresponding multiplier. Also in order to reduce the unnecessary operation, 1X multiple creation is added. In order to estimate the proposed serial decimal fixed-point multiplier, synthesis is implemented using Design Compiler. Synthesis results show that the delay of proposed multiplier is reduced by 2.8% and the area is increased by 0.22%, compared to the existing serial decimal multiplier.