Design of 6-Bit 2Gs/s Flash CMOS A/D Converter

YOON KWANG SUB

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Design of 6-Bit 2Gs/s Flash CMOS A/D Converter

YOON KWANG SUB

초록

This paper describes a 6bit 2Gs/s flash CMOS A/D converter with low power comparator. Power dissipation was decreased by control of the power at Bi-stable circuit.

제목: Design of 6-Bit 2Gs/s Flash CMOS A/D Converter

제목 (타언어): Design of 6-Bit 2Gs/s Flash CMOS A/D Converter

저자: YOON KWANG SUB

학회명: 반도체 학술대회