A Power-Efficient Transmitter Design for 3D-Stacked Memories in 28-nm CMOS Technology

초록

High-bandwidth memory (HBM) interfaces are critical components in future computing systems, demanding both high data rates and energy efficiency. In this work, we introduce an energy-efficient transmitter design for HBM I/O interfaces using advanced 28-nm CMOS technology. The proposed HBM transmitter design could minimize the power consumption of the I/O interface across multi-drop through-silicon via (TSV) channels. We propose a novel dual-edge boosted pre-driver circuit that significantly enhances the slew rate and maintains signal integrity under severe process-voltage-temperature (PVT) variations. Through the simulation of a 12-stacked TSV channel with a total capacitance of 1 pF, the proposed transmitter is validated with a power consumption of 2.18 mW, achieving a data rate of 11 Gb/s. The energy efficiency of our transmitter reaches 0.198 pJ/b/pF, presenting a promising solution for an energy-efficient and high-speed HBM I/O interface.

키워드