A Resolution Reconfigurable Hybrid ADC with Register-switching Method for Bio-signal Processing

초록

paper presents a low-power, highresolution hybrid CMOS ADC with a reconfigurable architecture for bio-signal processing. The hybrid architecture of the proposed ADC contains two exclusive substructures, namely successive approximation register (SAR) structure for the 8-bit most significant bit (MSB) and single-slope (SS) structure for the reconfigurable least significant bit (LSB). Reconfigurability is implemented via the SS block, which includes a 10-clock counter, reconfigurable binary counter, SS control circuit, and Done generator circuit The ADC was implemented in a standard CMOS n-well 28-nm 1-poly 8-metal process. The measurement results demonstrate a power consumption of 14.5 & mu;W (analog and digital power of 4.2 & mu;W and 10.3 & mu;W, respectively), effective number of bits (ENOB) of 12.4 bit, DNL/INL of & PLUSMN;0.96 LSB and & PLUSMN;0.92 LSB, and figure of merit (FoM) of 99.1 fJ/step.

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