A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier

Sung, Jae-hyeon; Yoon, Kwang-sub

doi:10.1145/3194554.3194641

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A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier

Sung, Jae-hyeon;
Yoon, Kwang-sub

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초록

This paper describes the 4th-order feedback delta-sigma modulator with only one reconfigurable amplifier. The modulator is designed with 180nm CMOS standard process. The measurement results demonstrate the power dissipation of 352uW, peak SNDR of 82.41dB and the ENOB of 13.4bits with an input signal frequency of 250Hz, a sampling frequency of 128 kHz, an input signal bandwidth of 1kHz, and an oversampling rate of 64.

키워드

CMOS; Delta-Sigma Modulator; Low power; reconfigurable amplifier

제목: A CMOS Low Power 4th-Order Delta-Sigma Modulator with One Reconfigurable Amplifier

저자: Sung, Jae-hyeon; Yoon, Kwang-sub

DOI: 10.1145/3194554.3194641

발행일: 2018

유형: Proceedings Paper

저널명: Proceedings of the IEEE Great Lakes Symposium on VLSI

페이지: 471 ~ 474