A 10-Bit 100MS.s CMOS ADC with Low Power MDAC

YOON KWANG SUB

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A 10-Bit 100MS.s CMOS ADC with Low Power MDAC

YOON KWANG SUB

초록

In this paper, a fully differential low power 10-bit 100MS/s pipeline CMOS A/D converter is proposed. A low power MDAC (Multiplying digital to Analog Coverter) that includes a low power opamp with switching technique is presented to minimize a power dissipation of the A/D converter.

제목: A 10-Bit 100MS.s CMOS ADC with Low Power MDAC

제목 (타언어): A 10-Bit 100MS.s CMOS ADC with Low Power MDAC

저자: YOON KWANG SUB

학회명: International SoC Design Conference