Extraction of RC Circuit Models from multi-level Interconnects for Giga-bit Era

초록

In this paper, we report a method of extracting RC circuit models from a complex three-dimensional interconnect structure for a full-chip simulation. Since it is computationally very expensive to simulate the circuit behavior of todays multi-level interconnects as a whole, we propose a method to partition the whole chip under consideration into small sub-circuits and then simulate each subcircuit in an individual manner. In this exemplary work of a ROM circuit with four words of four bits, we decompose the layout of the ROM array into four sub-layouts and extract capacitances and resistances in the sub-layout. For numerical calculation of the capacitances and resistances, Laplaces equation was solved over inter-layer dielectrics and conductors by finite element method (FEM).