A Study on the Expension of 4-Digit Cmos Quaternary to Analog Converter

초록

This paper describes a 3.3V low power 4 digit CMOS ternary to analog converter (QAC) designed with a neuron MOS down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source at LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6MHz and a power dissipation of 1mW with a single power supply of 3.3V for a double poly four metal standard CMOS 0.35㎛ n-well technology.