A Pass-Transistor Logic-Based Hybrid Approximate Full Adder Composition with Reduced Error

초록

Approximate computing has emerged as a promising low-latency and low-power solution for error-tolerant computing applications. Especially, the approximate adder can offer a significant reduction of the silicon area and power consumption compared to an accurate adder. This paper proposes an error-reduced 8-bit CMOS approximate adder with a novel composition of approximate full adders, which replaces the lower 4-bit least significant full adder with various inaccurate full adders. The implementation and its measurement demonstrate that our proposed composition reduces the latency, area, and power consumption by up to 25.50%, 25.42%, and 33.79% respectively, compared to the accurate 8-bit ripple carry adder, while achieving a low mean error distance (MED) of 2.13. © 2025 IEEE.

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