3개의 비교기를 이용한 스탭당 2비트의 10비트 SAR ADC 설계

초록

The proposed 10-bit SAR ADC is capable of generating two bits per one cycle which can be determined by three comparators within two-bit flash ADC and control logic. The conventional 10-bit capacitance DAC(digital-to-analog converter) with a split capacitor is employed to drive the input signal to three comparators. The proposed SAR ADC achieved SNDR of 60.1dB at sampling clock of 10Msps and input signal of 10kHz. The ADC consumes 280uW with the power supply of 1.8V and the effective number of bit of 9.6 bit. It results in the FoM(Figure-of-Merit) of 36.5 fJ/step