Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture

초록

This paper presents a four-way row-splitting architecture for layered low-density parity-check (LDPC) decoder. Based on the proposed method, an efficient partially parallel pipelined QC-LDPC decoder is proposed. The synthesis results using TSMC 40-nm standard cell CMOS technology show that the proposed decoder achieves the maximum required throughput of 7.05 Gb/s and outperforms its predecessors in terms of area efficiency.

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