A 3.2-12.8 Gbps 16-Lane PRBS Generator for Memory Interface Testing in 28nm CMOS

초록

This paper presents a 16-lane Pseudo-Random Binary Sequence (PRBS) generator designed in a 28nm CMOS process. The proposed PRBS generator architecture implements multiple random data outputs by incorporating XOR operations from multiple flip-flop (FF) circuits, enabling the PRBS data pattern for memory interfaces. To enhance the data signal integrity for a wide range of frequency operation, the proposed PRBS circuit is designed to synchronize the inverse phase of the clock signal when generating multiple PRBS outputs. The proposed PRBS generator can provide a high-speed and low-power built-in self-test (BIST) schemes for high-performance memory subsystems and testing. © 2025 IEEE.

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