Device optimization of Multiple-channel FET with 2-D Poisson-Schroinger Solver

  • WON TAEYOUNG

초록

Recently, a double-gate (DG) structure has attracted a great deal of attention for the application of sub-40nm MOSFET. Among the proposed variations of DG MOSFETs, a self-aligned DG MOSFET structure such as Fin-FET is one of the most promising candidates for implement a nano-scale planar MOSFET [1, 2]. The conven-tional FinFET, however, has a shortcoming in that a sophisticated multi-fin layout is required for enhancing the drive current. Furthermore, due to the pitch limit of lithography tools, it is difficult to have pitch narrower than the design rule, which limits the effective use of the active area for FinFET. Therefore, Multiple-channel FET [3] is a good alternative choice because it can be fabricated without relying on the lithographical limit for active patterning. Multiple-channel FET is a new device structure wherein center gate is placed at the center of the fin to form a multi-channel. In this paper, we report our quantum-mechanical investigation on Mulitple-channel FET in an effort to optimize the device structure.

제목
Device optimization of Multiple-channel FET with 2-D Poisson-Schroinger Solver
저자
WON TAEYOUNG
학회명
International Microprocesses and Nanotechnology Conference