Low Temperature Submicron-Pitch Cu/SiO2 Hybrid Bonding via Dual Selective Interface Activation Strategy

초록

Currently, semiconductor packaging technologies are attracting significant attention due to the scaling limitations in front-end processes, as represented by the slowing of Moore’s law. In semiconductor packaging, the primary purpose is to establish interconnections between integrated circuit chips and the substrate. Conventional bump-based interconnection approaches employing micron-sized solder bumps hinder further scaling toward submicron-pitch Cu pads required for hybrid bonding technologies. In this study, a dual selective interface activation strategy is proposed to achieve a reliable submicron-pitch Cu/SiO2 hybrid bonding (HB) under low-temperature conditions (< 250 °C). The process integrates Au electroless deposition (Au-ELD) on Cu pads with 3-aminopropyltriethoxysilane (APTES)-based surface modification of the SiO2 dielectric. Direct Cu?Cu and SiO2?SiO2 bonding was achieved annealing two-bonded chips at 250 °C, yielding void-free interfaces and strong adhesion. Accordingly, this dual interface activation strategy successfully demonstrated the low temperature hybrid bonding technology applicable to the next-generation fine-pitch 3D integration for advanced semiconductor packaging. - This research was partly supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (grant No. RS-2025-25436607 and RS-2025-25396489), and by the INHA UNIVERSITY Research Grant. Keywords: Advanced packaging; Cu/SiO2 hybrid bonding; low temperature; Au-electroless deposition; silane functionalization.