SPIRE-HBM: A Sub-Pseudo-Channel Architecture for HBM4 Bandwidth Scaling

초록

High-frequency HBM4 suffers from bandwidth underutilization because each pseudo channel (pCH) has only two bank groups within a selected Stack ID (SID), making BG interleaving insufficient to hide long column-to-column timing constraints. Existing industrial approaches mitigate this problem by adding DQ TSV resources, increasing implementation cost. We propose SPIRE-HBM, a sub-pseudo-channel-based HBM4 architecture that restores seamless BG-interleaved reads without increasing DQ TSVs. SPIRE-HBM partitions each 32-DQ pCH into two 16-DQ sub-pCH data paths across Stack IDs and doubles the burst length to preserve conventional access granularity. The longer burst provides sufficient column-command separation for two-BG interleaving, shifting the limiting column timing from tCCDL to tCCDS. Our evaluation shows that SPIRE HBM improves performance by up to 1.10× for Llama3-8B and 1.15× for synthetic workloads over HBM4. In addition, at 12.8 Gbps, SPIRE-HBM achieves performance comparable to a TSV-doubled HBM4 baseline while retaining the DQ TSV count. © 2002-2011 IEEE.

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