Design of an Adder and Multiplier on GF(p) Using T-gate

  • Kim Heung Soo

초록

In this paper, we implemented adder and multiplier using current mode T-gate in GF(p). The T-gate consists of current mirror and transmission gate, the implemented 3, 4-valued T-gate used adder and multiplier in GF(p). We designed its under 1.5um CMOS standard technology. The circuits is 15uA unit current, and 3.3V VDD coltage using SPICE. The proposed current mode CMOS operator have a advantage of module by T-gate's arrangement, and so we easily implement multi-valued operator

제목
Design of an Adder and Multiplier on GF(p) Using T-gate
저자
Kim Heung Soo
학회명
The 2003 International Technical Conference on Circuits/Systems, Computers and Conmmunications