A CMOS 10-bit SAR ADC with Threshold Configuring Comparator for 5 MSBs

초록

This paper describes a CMOS 10-bit Successive Approximation Register (SAR) Analog to Digital Converter(ADC) using TCC(Threshold Configuring Comparator) for the 5MSBs. This architecture enables SAR to simplify C-DAC and reduce power consumption. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 750um х 700um. It consumes 53uW and achieves an ENOB of 9.7 bits at sampling frequency 10MS/s, power supply of 1.8V, and reference of 1.2V. The Figure of Merit (FOM) is simulated to be 6.37fJ/step.