A Pulse Width Modulation-Based Spike Generator to Eliminate Timing Errors in Spiking Neural Networks

초록

This paper proposes a novel spike generator for processing in memory (PIM) technology. Most of the electronics today utilize a von Neumann architecture. The von Neumann architecture suffers from the separation of memory and processor. This architecture delays data transfer between memory and processor. To overcome the issues, we utilize the spiking neural network (SNN) that combines memory and processor. SNN can be classified into voltage-based, current-based, and time-based architectures, each with its own pros and cons. Time-based SNN suffers from timing issues. To address the timing sensitivity of time-based neuron SNN, this paper proposes a PWM-based SNN. The PWM-based SNN utilizes pulse width-based logic to overcome timing sensitivity. © 2025 IEEE.

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