The Design of the Ternary Logic Gates Using Threshold Inverter with Neuron MOS

초록

In this paper, the ternary logic gates have been proposed. The ternary logic gates consist of n-channel pass transistors and threshold inverter with neuron MOS(vMOS) on voltage mode. The ternary logic gate was designed with transmission function using threshold inverter, the threshold inverters are designed by using the DLC(Down Literla Circuit) that has various threshold voltages. The vMOS pass transistor is very suitable the gate to multiple-valued logic(MVL) and this pass transistor has the input signal of the multi-level by the vMOS threshold gate. In this paper, these circuits are used 3.3V low power supply voltage and 0.35um process parameter, and also represented HSPICE simulation result.