Design of a 10-bit SAR A/D Converter with 2-bit/step and Threshold Configuring Comparator

초록

Configuration of the entire circuit is a Threshold Configuring Comparator to determine the digital bits of 5MSBs, a capacitor D/A converter for 5LSBs and a clock double circuit reducing the clock cycles for data conversion then, it increased the speed of operation. Using Threshold Configuring Comparator, reduced the number of comparator in conventional 2bit/step SAR A/D converter, it reduced the capacity of the capacitor D/A converter. In 5MSBs, the digital code is determined by using Threshold Configuring Comparator. Threshold Configuring Comparator connects the current path to the input pair by changing the offset, and it is moved on digital code of 5MSBs sequentially. 5LSBs is determined by changing the reference voltage to the switching of the capacitor D/A converter. In this manner, it reduced the capacitance of the capacitor D/A converter, dynamic power consumption and chip area. A clock double circuit reduced cycles of the external clock to half, it increased the operation speed by 2bit/step.