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초록
This paper introduces a low power multiplier without deterioration of speed performance by the proposed Algorithm for Power-Delay-Product and optimization through Complementary Pass Transistor Logic
- 제목
- Low Power Multiplier Design using the Pass Transistor Delay Profile
- 제목 (타언어)
- 패스 트랜지스터 지연특성을 이용한 저전력 곱셈기 설계
- 저자
- CHUNG DUCK JIN
- 학회명
- The 2004 International Technical Conference on Circuit/Systems, Computers and Communications(ITC-CSCC2004)