VLSI implementation of a SOVA decoder for 3GPP standard turbo code with efficient ACS unit

효율적인 ACS 유닛을 가진 3GPP 터보코드를 위한 SOVA 복호기의 VLSI 구현
  • CHUNG DUCK JIN

초록

A new path metric normalization technique is presented for a Soft-output Viterbi Algorithm(SOVA) decoder for 3GPP standard turbo codes. Add-compare-select(ACS) unit is known to be the main critical path in a cinventional Viterbi decoder and in a SOVA decoder as well. In order to resolve the bottleneck in the ACS unit and prevent the reliability information from being truncated during the path metric normalization process, we suggest new normalization technique and employ it to design the SOVA decoder for 3GPP compiled turbo codes by using Altra Flex10K100 Device.

제목
VLSI implementation of a SOVA decoder for 3GPP standard turbo code with efficient ACS unit
제목 (타언어)
효율적인 ACS 유닛을 가진 3GPP 터보코드를 위한 SOVA 복호기의 VLSI 구현
저자
CHUNG DUCK JIN
학회명
3rd International Conference on Information, Comunications, and Signal processing