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초록
In this paper, we report a novel method for effectively reducing the amount of calculation for a deposition rate at a specific level-set node. The proposed algorithm makes it possible to reduce the number of level-set nodes from 15,000 down to 5,000 for the same accuracy and convergence. Furthermore, the total CPU time for simulating the surface evolution on the wafer during the plasma deposition process has been reduced approximately by one-ninth of the required CPU time in accordance with the traditional level-set method.
- 제목
- Modeling of Deposition Process by Level Set Method
- 저자
- WON TAEYOUNG
- 학회명
- Technical Proceedings of the fourth International Conference on Modeling and Simulation of Microsystems