Design of an Area-Efficient and Error-Reduced CMOS Approximate Adder

초록

Approximate adders have emerged as promising solutions in facilitating error-tolerant computing applications where a degree of imprecision is acceptable. Approximate adders offer significant improvements in terms of area utilization and power consumption compared to their exact counterparts. This paper proposes a novel design of an 8-bit CMOS approximate adder that utilizes a 6-bit least significant inaccurate sub-adder using approximate full adder (AFA) and copy adder with an error reduction unit (ERU). The implementation results demonstrate that our proposed approximate adder improves area, power, and delay by up to 20%, 9%, and 24%, respectively compared to the conventional AFA-based 8-bit adder while maintaining a low MED of 9.57. © 2024 IEEE.

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