Twiddle Factor Generator Architecture for Number Theoretic Transform

초록

The computational complexity and the large off-chip memory access of the Number Theoretic Transform (NTT) in Fully Homomorphic Encryption (FHE) are the most dominant processes in terms of the overall execution time. Furthermore, it becomes even more complicated with the Residue Number System (RNS) due to the requirement of multiple executions with different moduli. Therefore, modern RNS-based homomorphic encryption hardware architectures need the twiddle factor sets to be frequently changed from off-chip memory. To address this problem, this paper proposes an FPGA implementation of a twiddle factor generator for NTT, which can reduce off-chip memory access for different twiddle factor sets.

키워드