Design of a 5.2GHz/2.4GHz CMOS Dual Band Frequency Synthesizer for WLAN

YOON KWANG SUB

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Design of a 5.2GHz/2.4GHz CMOS Dual Band Frequency Synthesizer for WLAN

YOON KWANG SUB

초록

This paper presents a Phase Locked Loop(PLL) based frequency synthesizer (FS) which is designed in a standard 0.18um CMOS 1P6M process for 5.2GHz/2.4GHz dual band wireless applications.

제목: Design of a 5.2GHz/2.4GHz CMOS Dual Band Frequency Synthesizer for WLAN

제목 (타언어): Design of a 5.2GHz/2.4GHz CMOS Dual Band Frequency Synthesizer for WLAN

저자: YOON KWANG SUB

학회명: International SoC Design Conference