병렬 진화알고리즘 프로세서의 VLSI 구현

VLSI Implementation of Parallel Genetic Algorithm Processor
  • CHUNG DUCK JIN

초록

This paper describes the high-performance Pallel Genetic Algorithm Processor(PGAP) for reducing computation time. the proposed processor is based on steady-state model among continuous gerneration model. It used modified tourmant selection and special survival condition. Also we proposed hardware oriented migration method that is just right for hardware.

제목
병렬 진화알고리즘 프로세서의 VLSI 구현
제목 (타언어)
VLSI Implementation of Parallel Genetic Algorithm Processor
저자
CHUNG DUCK JIN
학회명
IDEC