Topography Simulation for Wafer-scale Structural Anaysis

초록

we report a novel topography simulation scheme for numerical analysis of complex device structure. The proposed method guarantees computational efficiency with affordable memory size due to efficiency in implementing the cell list. The simulation result of the ROM structure is required memory size of 8.133Mbytes. The proposed scheme was employed for the calculation of capacitance of a test structure having 4 metal lines embedded with two types of non-planar dielectric layer. The simulation result exhibited the capacitances between metal lines embedded in different layer increase, while the lateral capacitances between metal lines in the same layer decrease. It is considered that the cell advancing method is very suitable to figure out the profile during the deposition/etching process of nano-scale processes.