VLSI Implementation of Parallel Genetic Algorithm for Optimization Problems

초록

In this paper, we proposed the high-performance parallel Genetic Algorithm Processor (GAP) for reducing computation time. Based on steady state model among continuos generation model, the proposed parallel GAP used modified tournament selection, as well as special survival condition. In order to implement efficient hardware archicture, we use pipelined structure based on handshaking protocol. In addition, our design was applied the parallelisms of coarse-grain and fine grain for parallel and distributed processing in the pursuit of even better performance than the single GAP. In this paper the proposed parallel GAP is implemented on the PCIGEN10K board with two EFP10K100A240-1 devices. The proposed parallel GAP (2-processors) incresed the speed of finding optimal solution by about 50% more than the single GAP.