Node Elimination Method for Optimal RLC Parasitic Calculation

초록

In this paper we propose a realizable RLC-in-RLC-out technique to reduce parasitic parameters. The proposed technique is an efficient MOR (Model Order Reduction) method, which makes it possible to control the rise and delay time errors within the limit corresponding to the maximum frequency of operation. In addition, the equivalent circuit with reduced number of node elements derived from the proposed algorithm does conserve the passivity due to the use of zero-th or first order approximation.The proposed algorithm from node elimination is based on TICER (Time Constant Equilibration Reduction) approach. The reduction is achieved by eliminating the so-called quick nodes which have time constant less than the user-defined time constant. The nodal time constant is a maximum value between the RC time constant and LC time constant. Once the node is eliminated, new admittances are added to the neighboring nodes. It should be noted that the nodal time constant should be updated repeatedly while the reduction procedure continues until all the quick nodes are eliminated completely.In our exemplary case, the circuits with 48 to 19,600 elements were efficiently reduced with our proposed scheme, which is thereafter simulated with a SPICE circuit simulator. For exemplary circuits, one of which has 986 elements and the other of which has 19,600 elements, the simulation revealed that there arise only 1.3% error at the 68% reduction rates, while we have approximately 1% error rate at 97% reduction rates, respectively. The simulation results imply that the proposed method can guarantee relatively a high reduction ratio even with the specified frequency and provide quite an accurate result with reducing the CPU time tremendously for circuit designers.