Efficient Multiplier Architecture Using Optimized Irreducible Polynomial over GF (3^n^3)

초록

In this paper, multiplication algorithm over GF is presented and method of constructing a multiplier is described. The architecture is based on a modified version of the Karatsuba-ofman algorithm(KOA) to be applied to the multiplication of polynomial over . By determining optimized field polynomials of degree three, the last stage of the KOA and the module reduction can be combined. Finite fields are referred to as composite fields. This is parallel canonical basis multiplier with low gate counts and low delay. The architectures are highly modular and well suited for VLSI implementation.