글리치 억제 회로를 이용한 10비트 110MHz D/A 변환기 설계

초록

This paper describes a 3.3V-110MHz 10 bit CMOS current-mode Digital to Analog Converter(DAC) with a 6 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors(INL/DNL) caused by random and system errors are reduced by the proposed new double centroid sequencing methodology. A new deglitch circuit is proposed to minimize the glitch energy. The simulation results show a conversion rate of 110MHz, DNL/INL of ∂0.5LSB / ∂0.8LSB, a glitch energy of 10.5pV?ec , and a power dissipation of 126mW at 3.3V.