A novel approach for wafer defect pattern classification based on topological data analysis

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초록

In semiconductor manufacturing, wafer map defect pattern provides critical information for facility mainte-nance and yield management, so the classification of defect patterns is one of the most important tasks in the manufacturing process. In this paper, we propose a novel way to represent the shape of the defect pattern as a finite-dimensional vector, which will be used as an input for a neural network algorithm for classification. The main idea is to extract the topological features of each pattern by using the theory of persistent homology from topological data analysis (TDA). Through some experiments with a simulated dataset, we show that the proposed method is faster and much more efficient in training with higher accuracy, compared with the method using convolutional neural networks (CNN) which is the most common approach for wafer map defect pattern classification. Moreover, it was shown that our method outperforms the CNN-based method when the number of training data is not enough and is imbalanced.

키워드

Topological data analysisPersistent homologyMachine learningConvolutional neural networkWafer map classificationSemiconductor manufacturingNEURAL-NETWORKIDENTIFICATIONRECOGNITION
제목
A novel approach for wafer defect pattern classification based on topological data analysis
저자
Ko, SeungchanKoo, Dowan
DOI
10.1016/j.eswa.2023.120765
발행일
2023-11-30
유형
Article
저널명
Expert Systems with Applications
231