10비트 CMOS 전류구동 D/A 변환기 설계

초록

This paper describes a 3.3V-110MHz 10 bit CMOS current-mode DAC designed with a 6 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors caused by random Errors and system errors have been reduced by the 2D hierarchical symmetrical centroid sequencing method and optimized parameters. Spurs due to the glitches also are reduced by the new deglitch circuit.